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dc.contributor.authorKundu, Santanu
dc.contributor.authorChattopadhyay, Santanu
dc.date.accessioned2020-07-23T15:36:29Z
dc.date.available2020-07-23T15:36:29Z
dc.date.issued2014
dc.identifierONIX_20200723_9781466565265_23
dc.identifier.urihttps://library.oapen.org/handle/20.500.12657/41758
dc.description.abstractAddresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.
dc.languageEnglish
dc.subject.classificationthema EDItEUR::T Technology, Engineering, Agriculture, Industrial processes::TJ Electronics and communications engineering::TJF Electronics engineering::TJFC Electronics: circuits and componentsen_US
dc.subject.classificationthema EDItEUR::T Technology, Engineering, Agriculture, Industrial processes::TJ Electronics and communications engineering::TJF Electronics engineeringen_US
dc.subject.classificationthema EDItEUR::U Computing and Information Technology::UY Computer scienceen_US
dc.subject.otherCircuits and Devices
dc.subject.otherMicroelectronics
dc.subject.otherComputer Engineering
dc.subject.otherENG
dc.subject.otherElectricalEngineering
dc.subject.otherSCI-TECH
dc.subject.otherCOMPUTERSCIENCE
dc.subject.otherINFORMATIONSCIENCE
dc.subject.otherSTM
dc.subject.otherArchitecture Design of Network – on- Chip
dc.subject.otherEvolution of NoC Architectures
dc.subject.otherInterconnection Networks in NoC
dc.subject.otherReconfigurable Network-on-Chip Design
dc.subject.otherSantanu Chattopadhyay
dc.subject.otherApplication Mapping on NoC
dc.titleNetwork-on-Chip
dc.title.alternativeThe Next Generation of System-on-Chip Integration
dc.typebook
oapen.identifier.doi10.1201/b17748
oapen.relation.isPublishedBy7b3c7b10-5b1e-40b3-860e-c6dd5197f0bb
oapen.imprintCRC Press
oapen.pages389
peerreview.anonymitySingle-anonymised
peerreview.idbc80075c-96cc-4740-a9f3-a234bc2598f1
peerreview.open.reviewNo
peerreview.publish.responsibilityPublisher
peerreview.review.stagePre-publication
peerreview.review.typeProposal
peerreview.reviewer.typeInternal editor
peerreview.reviewer.typeExternal peer reviewer
peerreview.titleProposal review
oapen.review.commentsTaylor & Francis open access titles are reviewed as a minimum at proposal stage by at least two external peer reviewers and an internal editor (additional reviews may be sought and additional content reviewed as required).


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