A Chip-Area-Efficient Baseband Processing Core for FMCW Radar-based Sensor Network Localization

Abstract

There exists a variety of industrial applications in local environments, with an increasing demand for low-power and high-precision local positioning solutions based on wireless sensor networks. The focus of developing autonomous and cooperative sensor nodes with localization functionality is on the localization accuracy and range, energy efficiency and the size of the sensor nodes. In this context special attention is paid to the sensor digital signal processing, where the main task is to perform a Fast Fourier Transform (FFT). In this work the design of the radix-4 DIF FFT algorithm and its optimization with respect to hardware implementation for low-power local positioning systems is introduced. Furthermore, an area-efficient digital implementation of a baseband processing core for autonomous wireless sensor nodes with localization functionality is presented. The challenge for designing the digital system was to reduce memory requirements towards a low cost hardware design in general, and particularly for an ASIC design. Reducing chip area implies lower energy consumption and helps saving implementation and production costs. The presented novel baseband processing system concept has been implemented and verified on an FPGA. For the application scenario of a two-sweep-measurement system, an ASIC layout is designed based on the IBM 130 nm CMOS technology.