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    Strain-Engineered MOSFETs

    Proposal review

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    Author(s)
    Maiti, C.K.
    Maiti, T.K.
    Collection
    Knowledge Unlatched (KU)
    Language
    English
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    Abstract
    Currently strain engineering is the main technique used to enhance the performance of advanced silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Written from an engineering application standpoint, Strain-Engineered MOSFETs introduces promising strain techniques to fabricate strain-engineered MOSFETs and to methods to assess the applications of these techniques. The book provides the background and physical insight needed to understand new and future developments in the modeling and design of n- and p-MOSFETs at nanoscale. This book focuses on recent developments in strain-engineered MOSFETS implemented in high-mobility substrates such as, Ge, SiGe, strained-Si, ultrathin germanium-on-insulator platforms, combined with high-k insulators and metal-gate. It covers the materials aspects, principles, and design of advanced devices, fabrication, and applications. It also presents a full technology computer aided design (TCAD) methodology for strain-engineering in Si-CMOS technology involving data flow from process simulation to process variability simulation via device simulation and generation of SPICE process compact models for manufacturing for yield optimization. Microelectronics fabrication is facing serious challenges due to the introduction of new materials in manufacturing and fundamental limitations of nanoscale devices that result in increasing unpredictability in the characteristics of the devices. The down scaling of CMOS technologies has brought about the increased variability of key parameters affecting the performance of integrated circuits. This book provides a single text that combines coverage of the strain-engineered MOSFETS and their modeling using TCAD, making it a tool for process technology development and the design of strain-engineered MOSFETs.
    URI
    https://library.oapen.org/handle/20.500.12657/101554
    Keywords
    Strained Si; Substrate-Induced Strain Engineering in CMOS Technology; Gate Length; Process-Induced Stress Engineering in CMOS Technology; Power Consumption; Electronic Properties of Strain-Engineered Semiconductors; SCE; Strain-Engineered MOSFETs; Contact Etch Stop Layers; Noise in Strain-Engineered Devices; Mobility Enhancement; Biaxial Tensile Strain; Threshold Voltage; PTM; BTIs; NBTI; Metal Oxide Semiconductor Field Effect Transistor; Shallow Trench Isolation; HCI; Random Dopant Fluctuations; SiGe Layer
    DOI
    10.1201/9781315216577
    ISBN
    9781466503472, 9781138075603, 9781315216577, 9781466500556, 9781351832465, 9781466503472
    OCN
    862121374
    Publisher
    Taylor & Francis
    Publisher website
    https://taylorandfrancis.com/
    Publication date and place
    2018
    Grantor
    • Knowledge Unlatched - [...]
    Imprint
    CRC Press
    Classification
    Electronics: circuits and components
    Microwave technology
    Electrical engineering
    Pages
    320
    Rights
    https://creativecommons.org/licenses/by-nc-nd/4.0/
    • Imported or submitted locally

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    License

    • If not noted otherwise all contents are available under Attribution 4.0 International (CC BY 4.0)

    Credits

    • logo EU
    • This project received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 683680, 810640, 871069 and 964352.

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